Technical Field
The described embodiments generally relate to memory management in computing systems. More particularly, the embodiments relate to an apparatus for providing control of memory assigned to a processor for performing processing functions. More particularly still, the embodiments relate to power management control of such memory. The embodiments also relate to associated methods for providing such control, and to computer program products for implementing the methods.
The embodiments find applications in, in particular, mobile terminal systems, e.g., cell phones, smart phones, tablets etc.
Related Art
The approaches described in this section could be pursued, but are not necessarily approaches that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, the approaches described in this section are not prior art to the claims in this application and are not admitted to be prior art by inclusion in this section.
As a general development trend, processor speed, memory speed and memory capacity used for processing systems all increase with each new generation of processing system.
To increase memory speed, Double Data Rate (DDR) memory has been developed. DDR memory provides for data to be written to, and read from, the memory at high speeds. Additionally, the capacity of DDR memory used in, for example, embedded systems has been continuously increasing in order to fulfil performance needs.
However, with this increase in DDR memory capacity, an unwanted side effect is a commensurate increase in the DDR power consumption. As a result the autonomy of platforms, and thus the user experience, tends to be reduced. Since, for example, the battery life of a mobile platform using the DRR memory will also be reduced.
To combat this problem, the Low Power Double Data Rate (LPDDR) standard has been developed. This brings support to single-ended partial array self-refresh, which enables a reduction in power consumption. Additionally, the LPDDR2 standard brings support to bank and segment (LPDDR-S4) selective partial array self-refresh.
However, these low-power modes may be problematic because, for instance, the content retention of the memory areas set in these modes is not guaranteed.
In all Rich Operating Systems (OS) available on the market, such as Linux or Windows, and also in most existing OS, the management of the DDR memory refresh is not linked with the memory allocator. This is the case, for example, for both the Deep Power Down (DPD) and Partial Self Refresh (PASR) functions that are sometimes enabled in memory devices. Thus, in such OS control of memory refresh is not possible.
A further function, which is available in Linux, is a technique called “Memory Hotplug”. This enables some chunks of memory to be unplugged from the memory allocator point of view, and to plug some memory into the system. This method has been developed for servers, in order to be able to change some memory cards during maintenance operations without stopping the execution of the server. This method, nevertheless, is not particularly fast and requires a large amount of CPU (central processor unit) resources to implement. Thus, it is not suitable for application to embedded systems. A further problem with this method is implementation of a suitable decision as to when to plug in, or unplug, some part of the memory.
US2009/0109783 discloses a circuit that allows masking of memory to permit control of refresh of the memory.
It is an aim of the embodiments herein described to overcome or mitigate at least some of the above described limitations.